1. Field of Invention
The present invention relates to a prescaler. More particularly, the present invention relates to a dual-modulus prescaler (DMP) with dynamic circuit technique.
2. Description of Related Art
Frequency synthesizers are widely used in communication systems and microprocessors. A frequency synthesizer at least includes a frequency divider and a voltage-controlled oscillator (VCO). The operating frequency of the frequency synthesizer is limited by the frequency divider and the voltage-controlled oscillator (VCO).
A dual-modulus prescaler (DMP) is a leading example in the frequency divider. A prescaler at least includes two parts, i.e., a synchronous counter and an asynchronous counter. The synchronous counter is the most crucial block in the whole DMP. The synchronous counter works at maximum frequency and consumes most power. The speed of the synchronous counter limits the maximum operating frequency of the prescaler. A merge structure of NAND gates and D-Flip-Flops (DFFs) is popular. When the synchronous counter is implemented in P-precharge dynamic circuit techniques, there are two serial NMOS transistors in the discharge path, which results a large delay and lowers the operating frequency.
With a structure optimization of the synchronous counter, the operating frequency of the prescaler is increased and the power consumption thereof is lowered. Besides, there is a demand on an optimized structure of the DMP, which may reduce the propagation delay and have higher operating speed.
Therefore, there is a need for developing a DMP meeting the requirements.